In the evolution of integrated circuits in semiconductor technology, there has been a trend towards device scaling. Scaling or reducing the size increases circuit performance, primarily by increasing circuit speed, and also increases the functional complexity of the integrated circuits. The number of devices per chip has increased throughout the years. When integrated circuits contained only a small number of devices per chip, the devices could be easily interconnected in a single level. However, the need to accommodate more devices and increased circuit speed has led to the use of multi-level or multi-layer interconnects.
In a multi-level interconnection system, the area needed by the interconnect lines is shared among two or more levels, which increases the active device fractional area, resulting in increased functional chip density. Implementing a multilevel interconnect process to a fabrication scheme increases the complexity of the manufacturing process. Typically, the active devices (e.g., the transistors, diodes, capacitors and other components) are manufactured in the lower layers of wafer processing, often referred to as the Front End Of the Line (FEOL). After the active devices are processed in the FEOL, the multilevel interconnects are usually formed in the processing timeframe often referred to as the Back End Of the Line (BEOL).
As semiconductor devices continue to shrink, various aspects of multilevel interconnect processes are being challenged. The propagation delay of integrated circuits becomes limited by the large RC time delay of interconnection lines when minimum feature size is decreased below about 1 μm, for example. Therefore, the industry is tending towards the use of different materials and processes to improve multilevel interconnect implementations.
In the past, interconnect lines were made of aluminum. Now there is a trend towards the use of copper for interconnect lines because copper has a higher conductivity than aluminum. For many years, the insulating material used to isolate conductive lines from one another was silicon dioxide. Silicon dioxide has a dielectric constant (k) of approximately 4.0 or greater, where the dielectric constant value k is based on a scale where 1.0 represents the dielectric constant of a vacuum. However, now there is a move in the industry to the use of low-dielectric constant materials (e.g., having a dielectric constant k of 3.6 or less) for insulating materials. The change in both the conductive materials and insulating materials used in multilevel interconnect schemes is proving challenging and requires a change in a number of processing parameters.
Copper is a desirable conductive line material because it has a higher conductivity than aluminum. However, the RC (resistance/capacitance) time delay of copper conductive lines can be problematic, so low-dielectric constant materials are used to reduce the capacitive coupling and reduce the RC time delay between interconnect lines. However, copper easily migrates into low-dielectric constant materials, which can cause shorting and create device failures. To prevent this, liners are typically used to prevent the migration of copper into the adjacent low-dielectric constant material.
Some low-dielectric constant materials are porous, having a plurality of pores spaced throughout the dielectric material. Such porous low-dielectric constant materials may be deposited by chemical vapor deposition (CVD), or may be spun on and cured by heating to remove the solvent. Porous low-dielectric constant materials are advantageous in that they have a dielectric constant of 3.0 or less. Examples of such porous low-dielectric constant materials include porous SiLK™ and porous silicon carbonated oxide, as examples.
A prior art semiconductor device 100 is shown in FIG. 1A. A workpiece 102 is provided, wherein active components and transistors have been formed within the workpiece 102 in a FEOL process, for example. An insulating layer 104 has been formed over the workpiece 102, as shown. The insulating layer 104 may comprise borophosphosilicate glass (BPSG), as an example. A BEOL process utilizing copper and porous low-dielectric constant materials will next be described.
A first porous low-dielectric constant material 106 is deposited over the insulating layer 104, as shown. A hard mask 108 may be deposited over the first low-dielectric constant material 106. The hard mask 108 and the first low-dielectric constant material 106 are patterned with a pattern 112 for conductive lines, for example. In the example shown, the pattern 112 is a single damascene pattern for one level of metal lines. A liner 116 is deposited over the hard mask 108 and over the sidewalls 114 of the first low-dielectric constant material 106. The liner 116 also covers the top surface of the exposed insulating layer 104. The liner 116 is conductive and may comprise a first liner and a seed layer deposited over the first liner. The first liner may comprise Ta and/or TaN, and the seed layer may comprise copper. A conductive material 118 is deposited over the conductive liner 116. The conductive material 118 preferably comprises copper and may also cover the top surface of the hard mask 108.
The workpiece 102 is exposed to a chemical mechanical polish (CMP) process to remove excess conductive material 118 and excess conductive liner 116 from the top surface of the hard mask 108. Optionally, the hard mask 108 may also be removed from over the top surface of the first low-dielectric constant material 106, (not shown).
An optional cap layer 120 may be deposited over the hard mask 108 and conductive material 118 as shown. A second low-dielectric constant material 122 is then deposited over the cap layer 120. In the examples shown, the second low-dielectric constant material 122 has a greater thickness than the first low-dielectric constant material 106, because a dual damascene pattern will be formed within the second low-dielectric constant material 122.
A hard mask 124 is deposited over the second low-dielectric constant material 122. The hard mask 124 and second low-dielectric constant material 122 are then patterned with a dual damascene pattern 126. The dual damascene pattern 126 includes a narrower portion in which vias 139 will be formed, and a wider portion in which conductive lines 138 will be formed. The vias 139 connect the upper conductive lines 138 with the underlying conductive lines 118. Note that the dual damascene pattern 126 also extends through the cap layer 120 so that electrical contact may be made by the via of the dual damascene pattern 126 to the underlying conductive line 118.
A conductive liner 134/136 is then deposited over the patterned hard mask 124 and second low-dielectric constant material 122. The liner 134/136 includes a liner 134 deposited over the sidewalls 128 and horizontal surface 130 of the second low-dielectric constant material 122 and exposed top surface of the conductive lines 118. The liner 134 may comprise Ta, a bilayer of Ta and TaN, or other materials, as examples. The liner 134/136 includes a seed layer 136 comprising copper deposited over the liner 134. The liner 134/136 is also deposited on the top surface of the hard mask 124, for example, not shown.
A conductive material 138/139 comprising copper is then deposited over the seed layer 136 to fill the patterned second low-dielectric constant material 122 and other patterned areas of the cap layer 120 and hard mask 124. The workpiece 102 is then exposed to another CMP process to remove the conductive material 138/139 and liner 134/136 from the top surface of the hard mask 124 and form conductive lines 138 and vias 139 within the second low-dielectric constant material 122.
The low-dielectric constant materials 106 and 122 comprise porous materials. When these porous low-dielectric constant materials 106 and 122 are patterned, the sidewalls 114 and 128 of the low-dielectric constant materials 106 and 122, respectively, appear as shown in an exploded view in FIG. 1B. Because the pores 132 of the two low-dielectric constant material layers 106 and 122 are similar, only one exploded view is shown, for purposes of discussion. The pores 132 of the first low-dielectric constant material 106 and second low-dielectric constant material 122 are opened in the region along the sidewalls 114 and 128 and also along horizontal surface 130 of the second low-dielectric constant material 122 to expose an inner surface 133 of each pore 132 along the sidewalls 114 and 128.
FIGS. 1C and 1D illustrate an exploded view of the deposition of the conductive liner 134/136 and conductive fill material 138/139 along the sidewall 128 of the second low-dielectric constant material 122, respectively. While these cross-sectional views will be described with respect to the pores 132 along the sidewall 128 of the second low-dielectric constant material 122, the same phenomena may be seen along the sidewall 114 of the first low-dielectric constant material 106 and along the horizontal surface 130 of the second low-dielectric constant material 122.
In this prior art process, when the liner 134 is deposited within the patterned second low-dielectric constant material 122, the liner 134 has poor step coverage and does not completely fill the pores 132 along the sidewall 128 that have been opened. Rather, as shown in FIG. 1C, the inner surfaces 133 of the pores 132 along the sidewall 128 remain unlined and unfilled. When the seed layer 136 is subsequently deposited over the liner 134, again, the seed layer 136 is not deposited on the inner surface 133 of the pores 132, and the pores 132 remain unlined along the inner surface 133.
FIG. 1D illustrates a cross-sectional view of a close-up of the sidewall 128 after the conductive material 138/139 comprising copper has been deposited within the patterned second conductive layer 122. The conductive material 138/139 fills the pores 132 along the sidewall 128 that has not been lined by the seed layer 136 and liner 134. The conductive material 138/139 makes direct contact with the inner surface 133 of the pores 132 along the sidewall 128. Because copper 140 from the conductive material 138/139 migrates or diffuses very quickly within the dielectric material 122, fast diffusion paths are created for the copper-containing conductive material 138/139 into the second low-dielectric constant material 122. The copper diffusion channel that is created within porous low-dielectric constant materials 122 and 106 causes reliability problems in semiconductor devices 100, causing shorts and devise failures.
FIGS. 2A through 2D illustrate a prior art method of attempting to prevent copper from migrating into porous low-dielectric constant materials through pores along the sidewalls of patterned porous low-dielectric constant materials. The same structure having a single damascene layer and a dual damascene layer is shown in FIGS. 1A through 1D as is shown in FIGS. 2A through 2D. Like numerals are used in FIGS. 2A through 2D with respect to FIGS. 1A through 1D to describe the various elements and common components shown.
Referring first to FIGS. 2A and 2B, in this prior art process, a plasma enhanced chemical vapor deposition (PECVD) oxide spacer 242 is formed along the sidewalls 214 and 228 of the low-dielectric constant materials 206 and 228 prior to filling the damascene patterns with a conductive liner and conductive material. However, as shown in FIGS. 2C and 2D, the PECVD oxide spacer 242 has poor step coverage of the pores 232, and does not line the inner surface 233 of the pores 232 that are exposed on the sidewalls 214/228. Therefore, the inner surface 233 of the pores 232 are not protected from the copper of the subsequently deposited conductive material 218 and 238/239, as shown in FIG. 2D, and a path of diffusion is created for the copper 240 within the conductive material 218 and 238/239. Copper 240 thus diffuses into the pores 232 of the porous low-dielectric constant materials 206 and 222, causing reliability problems, shorts, and device failures.
Therefore, what is needed in the art is a method and structure for preventing copper migration and diffusion into porous low-dielectric constant materials of semiconductor devices.